The signal path of the TimeRunner starts with a clock which is generated internally or is injected from an external source. The clock is split into the 4 cascaded channels' clock dividers, creating even /2, /4, /8, /16 divisions when seen from top to bottom.
In addition each channel has two selectable logic circuits, an AND and a XOR gate. A switch or a gate voltage at the "logic in" determines if he logical result of the AND or the XOR is available at the channel's direct OUT.
How the logic works:
The output of each channel division is sent to the first logic input of both an AND and XOR logic chip. The second input of the AND and XOR logic chips is referred to as the SEED. The first channel Seed is always high unless the Seed Input Jack is used. The Seed input for the remaining channels is derived from either the AND or XOR logic output of the previous channel using the Channel Seed Switch.
Due to this relations and connections the channels interact and influence each other: if you change setting at channel 2, this will have an effect on channels 3 and then 4.
If you want to use the Timerunner as a clock divdier only, set all Seed-In switches and logic switches to "AND". Flipping the Channel 1 Logic Selector switch flips the output of Channel 1 to odd beats.
Clock generator: 2x square outputs
external clock in, reset in
channel 1; seed input, logic input, output
channels 2-4: logic input, output
3U Eurorack module, 12HP wide, 36.5mm deep
current draw is 45mA
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